1. Field of the Invention
The present invention relates to a synchronization circuit for performing a predetermined operation in response to a received sync signal, in particular, to a synchronization circuit to which an internal sync signal is not transmitted when transition of a plurality of received signals does not occur, and to a storage device having such a synchronization circuit.
2. Related Arts
A synchronization semiconductor storage device, which can be operated at high speed, includes an input circuit for latching an address signal and other control signals in response to a sync signal, such as a clock, received from the outside; a sense amplifier for detecting data in a memory cell; and a write amplifier for writing data to a memory cell.
Even when, for example, an address signal is skewed, by employing the above sync signal the entry of data is possible after the address signal has been established. Therefore, waste operation in an input circuit can be eliminated and the period of time that is required to establish an address signal can be shortened. Or, a system can rapidly fetch the data by operating a sense amplifier in response to a sync signal. In addition, the period of time that is required to establish a write data signal can be shortened by initiating the operation of a write amplifier in response to a sync signal. Therefore, processing for which a sync signal is used is indispensable when the speed of memory is to be increased.
The same procedures can be employed for a synchronization circuit, not limiting to the memory, which performs processing in accordance with a plurality of signals, which are supplied in response to a supplied sync signal.
However, even when there are no changes in input signals to which normally the circuit responds, the synchronized memory or the synchronization circuit continues to perform a predetermined operation in response to received sync signals, so that power is consumed wastefully.
In a case where there is no change in an address signal and a reading condition, even though the data have not been changed, a sense amplifier in a synchronized memory will detect data to read in the memory in response to a sync signal. Such operation when performed by the sense amplifier is mere repetition, which constitutes a waste of power.
In a case where there is no change in an address signal and in the data to be written, and when the writing condition is the same, even though the writing of the data to a target memory has been completed, a write amplifier in a synchronized memory performs a writing operation in response to a sync signal. The write amplifier merely repeats an operation that has been completed, which results in a waste of power.